Integrated circuits are manufactured as assemblies of various devices, such as multiple transistors that can make up a single chip and as multiple chips that can be included on a single wafer. In most processes for manufacturing integrated circuits, after individual devices, such as the transistors, have been fabricated on the silicon substrate, they are connected together to perform desired circuit functions. This connection process is generally referred to as “metallization,” and can be carried out using a number of different photolithographic and deposition techniques.
Due to the high level of integration of devices and the large number of circuits on a single chip, interconnections are often no longer made by means of a single level of interconnections. Instead, it can be necessary to provide at least two and sometimes more conductor interconnection levels, with each interconnection level having a pattern of wiring trenches being separated from the others by an insulating layer. Connections between these interconnection pattern levels and the various devices on a chip are then made by means of contact plugs, also referred to as vias, which are formed by etching a via hole through the insulating layers separating the devices and wiring trenches and then filling the via holes and trenches with a metal or other conductive material to connect the individual devices.
In general, the formation of conductive wiring patterns and vias is carried out by a process which includes depositing an insulating layer over an integrated circuit comprising numerous memory devices on a silicon wafer and then forming wiring trenches and via holes in the insulating layer by etching a pattern in the insulating layer to expose various portions of any number of the memory devices in the integrated circuit below, and filling the trenches and via holes with a conductive material. Chemical mechanical polishing is then often used to remove excess conductive material outside the trenches of the pattern formed in the dielectric material.
Various methods are used to form vias and wiring trenches in interlayer insulating materials for multilevel metal interconnection microelectronics. Such methods are known and referred to as damascene processes. It is often advantageous to fill both vias and trenches with a single metallization step. Such processes wherein the metal forming the vias and the metal forming the wiring trenches are deposited simultaneously are referred to as dual-damascene processes. However, even when the vias and trenches are metallized simultaneously, the processes still include two separate etching steps. In other words, the via holes and wiring trenches are separately etched.
The separate etching of the via holes and wiring trenches often leads to difficulty in achieving overlay alignment between the via holes and the trenches. The misalignment problem between trenches and vias in modern damascene processes has become more difficult to avoid with the decreasing minimum feature size necessitated by the increased demands of integration for high density semiconductor devices.
Accordingly, there is a need in the art for a method of forming interconnection systems for integrated circuits which avoids the misalignment or overlay alignment problem of connecting vias and wiring trenches, particularly in interlayer interconnection systems.